1.
Kaushik Velapa Reddy. Layered Verification Strategies for AI Accelerator Hardware: Matrix Engines and SRAM Buffers. JCSTS [Internet]. 2025 Jun. 6 [cited 2025 Aug. 7];7(5):786-95. Available from: https://al-kindipublishers.org/index.php/jcsts/article/view/9882